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Parallel Algorithms for Formal Logic Design Verification Based on Binary Decision Diagrams

Parallel Algorithms for Formal Logic Design Verification Based on Binary Decision Diagrams

Koichi Nagami

生駒 : 奈良先端科学技術大学院大学, 1995.3

Thesis / Diss.

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Total: 1
No. Printing year Location Call Number Material ID Circulation class Status Waiting

1

R000086

2

  • [IS]1995(8)

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Publication year

1995

Form

58p

Alternative title

二分決定グラフを用いた形式的論理設計検証における並列処理

Series title

奈良先端科学技術大学院大学情報科学研究科修士論文 ; 1995年3月

Note

学位記番号: 修第100号

授与年月日: 1995/03/24

学位の種類: 修士(工学)

学生番号: 0351082

Country of publication

Japan

Title language

English (eng)

Language of texts

English (eng)

Author information

永見, 康一 (ナガミ, コウイチ)

Subject

Logic Circuits

Computer Aided Design

Formal Design Verification

BDDs

Parallel Algorithms

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