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A placement and routing algorithm for a reconfigurable 1-bit processor array

A placement and routing algorithm for a reconfigurable 1-bit processor array

Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, and Yasuhiko Nakashima

生駒 : 奈良先端科学技術大学院大学, 2007.3

In-house publ.

Volume No.

Total: 1
No. Printing year Location Call Number Material ID Circulation class Status Waiting

1

  • TR

R005020

Details

Publication year

2007

Form

7 p.

Series title

Information Science Technical Report ; TR2007004

Country of publication

Japan

Title language

English (eng)

Language of texts

English (eng)

Author information

伴野, 充 (トモノ, ミツル)

中西, 正樹 (ナカニシ, マサキ)

山下, 茂 (ヤマシタ, シゲル)

中島, 康彦 (ナカシマ, ヤスヒコ)

ISSN

09199527