Regular Expression Timing Simulation of Logic Circuits Based on Implicit Manipulation of Finite Automata

Regular Expression Timing Simulation of Logic Circuits Based on Implicit Manipulation of Finite Automata

Toru Kawasaki

生駒 : 奈良先端科学技術大学院大学, 1995.3

Thesis / Diss.

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No. Printing year Location Call Number Material ID Circulation class Status Waiting

1

R000037

2

  • [IS]1995(3)

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Publication year

1995

Form

54p

Alternative title

有限オートマンの非明示的処理を用いた正則表現タイミングシミュレーション

Series title

奈良先端科学技術大学院大学情報科学研究科修士論文 ; 1995年3月

Note

学位記番号: 修第68号

授与年月日: 1995/03/24

学位の種類: 修士(工学)

学生番号: 0351027

Country of publication

Japan

Title language

English (eng)

Language of texts

English (eng)

Author information

川崎, 通 (カワサキ, トオル)

Subject

timing verification

finite automaton

binary decision diagram

timing simulation

regular expression

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