Contents Intro.

Timing-related defects are major contributors to test escapes and in-field reliability problems for nanoscale integrated circuits (ICs). Timing problems are caused by gross delay defects, resistive shorts and opens, as well as by delay variations induced by crosstalk, process variations, and power-supply noise. The complexity of today’s ICs and shrinking process technologies are also leading to prohibitively high test data volumes. As a result, the 2007 ITRS document predicted that the test data volume for integrated circuits will be as much as 38 times larger and the test application time will be about 17 times larger in 2015. The speaker will first present an overview of delay-testing techniques used today in industry. Basic concepts such as fault models, design-for-testability, and test-application methods will be covered. Next, the speaker will present emerging test techniques for defect screening, which uses the method of output deviations for handling unmodeled faults. A new gate-delay defect probabili

Details

Publication year

2009

Form

電子化映像資料(1時間22分6秒)

Series title

情報科学研究科・ゼミナール講演 ; 平成21年度

Note

講演者所属: 講演者所属: Department of Electrical & Computer Engineering, Duke University

講演日: 平成21年7月6日

講演場所: 情報科学研究科大講義室

Country of publication

Japan

Title language

English (eng)

Language of texts

English (eng)

Author information

Chakrabarty, Krishnendu