Virendra Singh
生駒 : 奈良先端科学技術大学院大学, 2013.6
Lecture ArchiveRelentless scaling of silicon fabrication technology coupled with lower design tolerances are making ICs increasing susceptible to wear-out related permanent faults as well as transient faults (soft errors). A well known technique for tackling both transient and permanent faults is redundant execution, specifically space redundancy, wherein a program is executed redundantly on different processors, pipelines or functional units and the results are compared to detect faults.
| No. | Printing year | Location | Call Number | Material ID | Circulation class | Status | Waiting |
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2013
電子化映像資料(1時間33分59秒)
情報科学研究科・ゼミナール講演 ; 平成25年度
講演者所属: Indian Institute of Technology Bombay
講演日: 平成25年6月26日
講演場所: 情報科学研究科大講義室L1
Japan
English (eng)
English (eng)
