内容紹介

While the synchronous-logic approach, a clock-based synchronization approach, is still the de facto approach in digital circuits, some design issues in a synchronous circuit become more and more challenging specifically when the semiconductor technology continues to down-scale for higher performance and higher circuit integration. These design issues include operation robustness (affected by delay variations), high power dissipation, high electromagnetic interference, etc. Conversely, the asynchronous-logic design approach, a clock-less handshake approach, is a promising alternative in alleviating such design issues in digital circuits. Unsurprisingly, as predicted by the International Technology Roadmap for Semiconductors (ITRS), asynchronous-logic is estimated to account for 17% total circuitry of an integrated circuit (IC) chip from now, and up to 49% in year 2024.

詳細情報

刊年

2010

形態

電子化映像資料(1時間30分0秒)

シリーズ名

情報科学研究科・ゼミナール講演 ; 平成22年度

注記

講演者所属: Nanyang Technological University

講演日: 平成22年11月19日

講演場所: 情報科学研究科大講義室L1

標題言語

英語 (eng)

本文言語

英語 (eng)

著者情報

Chong, Kwen-Siong