内容紹介

The prevalence of deep neural networks today is supported by a variety of powerful hardware platforms including GPUs, FPGAs, and ASICs. A fundamental question lies in almost every implementation of deep neural networks: given a specific task, what is the optimal neural architecture and the tailor-made hardware in terms of accuracy and efficiency? Earlier approaches attempted to address this question through hardware-aware neural architecture search (NAS), where features of a fixed hardware design are taken into consideration when designing neural architectures. However, we believe that the best practice is through the simultaneous design of the neural architecture and the hardware to identify the best pairs that maximize both test accuracy and hardware efficiency. In this talk, we will present novel co-exploration frameworks for neural architecture and various hardware platforms including FPGA, NoC, ASIC and Computing-in-Memory, all of which are the first in the literature. We will demonstrate that our co-exploration concept greatly opens up the design freedom and pushes forward the Pareto frontier between hardware efficiency and test accuracy for better design tradeoffs.

詳細情報

刊年

2022

形態

電子化映像資料(分秒）

シリーズ名

情報科学領域・コロキアム ; 2022年度

注記

講演者所属: Sustainable Computing Laboratory, Department of Computer Science and Engineering, University of Notre Dame (USA) / Boston Children’s Hospital (USA) / Kyoto Univ. (Japan)

講演日: 2022年11月21日 3限

講演場所: 情報科学棟 エーアイ大講義室(L1)

標題言語

英語 (eng)

本文言語

英語 (eng)

著者情報

SHI, Yiyu