Digital Library of Nara Institute of Science and Technology

Help Japanese
Login Exit

Search Result in Detail : Journals

Integration, the VLSI journal TOC PDF

Amsterdam : North-Holland

Related materials

:
Location Call Number Year of holding Holding volume Continuing acceptance
1 Digital Library 1995-1999 20-27  
2 Library (Stack) 1992-1998 14-24, 26  

Vol.27 No.2 1999年7月

Location Call Number Material ID Accepted on Binding status Status Waiting
1 Digital Library 4003062 Oct 14, 1999 0
PDF Multi-schedule design space exploration: an alternative synthesis framework / Dalkilic M.E., Pitchumani V. p. 87-112
PDF Generating new benchmark designs using a multi-terminal net model / Stroobandt D., Depreitere J., Campenhout J.J.V. p. 113-129
PDF Timing driven cell replication during placement for cycle time optimization / Neumann I., Post H.-U. p. 131-141
PDF Synthesis of low-power CMOS circuits using hybrid topologies / Gallant M., Al-Khalili D. p. 143-163
PDF Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance / Gao Y., Wong D.F. p. 165-178
PDF Assessing merged DRAM/Logic technology / Kim Y.-B.Y.-B., Chen T.W. p. 179-194

Vol.27 No.1 1999年1月

Location Call Number Material ID Accepted on Binding status Status Waiting
1 Digital Library 4002623 Feb 18, 1999 0
PDF Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay / Ramanathan S., Visvanathan V. p. 1-32
PDF Establishing latch correspondence for sequential circuits using distinguishing signatures / Mohnke J., Molitor P., Malik S. p. 33-46
PDF Provably good moat routing / Ganley J.L., Cohoon J.P. p. 47-56
PDF A timing-driven floorplanning algorithm with the Elmore delay model for building block layout / Koide T., Wakabayashi S. p. 57-76
PDF Maximum weighted independent sets on transitive graphs and applications / Kagaris D., Tragoudas S. p. 77-86

Vol.26 No.1-Vol.26 No.2 1998年12月

Location Call Number Material ID Accepted on Binding status Status Waiting
1 Digital Library 4002622 Feb 18, 1999 0
PDF Editorial(s) p. 1-3
PDF Testing with decision diagrams / Becker B. p. 5-20
PDF Delay fault models for VLSI circuits / Pomeranz I., Reddy S.M. p. 21-40
PDF Sequential test generators: past, present and future / Chang Kim Y., Saluja K.K. p. 41-54
PDF BIST for systems-on-a-chip / Wunderlich H.-J. p. 55-78
PDF High-level test synthesis: a survey / Ghosh I., Jha N.K. p. 79-99
PDF An approach to test synthesis from higher level / Inoue M., Fujiwara H. p. 101-116
PDF FTROM: A Silicon Compiler for Fault-tolerant ROMs / Gupta A., Chakraborty K., Mazumder P. p. 117-140
PDF Design of mixed-signal systems for testability - Theory Appl. / Agrawal V.D. p. 141-150
PDF Mixed-signal on-chip timing measurements / Soma M. p. 151-165
PDF IDDQ testing: state of the art and future trends / Ferre A., Isern E., Rius J., Rodrguez-Montanes R., Figueras J. p. 167-196
PDF On-line testing for VLSI: state of the art and trends / Nicolaidis M. p. 197-209
PDF A new approach in feature interaction testing / Nakamura M., Kikuno T. p. 211-223

Vol.25 No.2 1998年11月

Location Call Number Material ID Accepted on Binding status Status Waiting
1 Digital Library 4002596 Feb 8, 1999 0
PDF An approximation algorithm for the register allocation problem / Jansen K., Reiter J. p. 89-102
PDF Comparison of the VLSI cost/performance properties of two Reed-Solomon decoding algorithms / Jennings S.M., Kessels J. p. 103-110
PDF GreyHound: A methodology for utilizing datapath regularity in standard design flows / Nijssen R.X.T., van Eijk C.A.J. p. 111-135
PDF On the optimal four-way switch box routing structures of FPGA greedy routing architectures / Pan J., Wu Y.-L., Wong C.K., Yan G. p. 137-159
PDF High-level synthesis techniques for functional test pattern execution / Hong I., Kirovski D., Kornegay K., Potkonjak M. p. 161-180
PDF Index p. 181-182
PDF Other contents p. 183

Vol.25 No.1 1998年9月

Location Call Number Material ID Accepted on Binding status Status Waiting
1 Digital Library 4002453 Dec 25, 1998 0
PDF VLSI design in the 3rd dimension / Strickland S., Ergin E., Kaeli D.R., Zavracky P. p. 1-16
PDF Theoretical properties of LFSRs for built-in self test - pseudo-random techniques / Dufaza C. p. 17-35
PDF Accurate and efficient power simulation strategy by compacting the input vector set / Tsui C.-y., Pedram M. p. 37-52
PDF Systolic-based parallel architecture for the longest common subsequences problem / Luce G., Myoupo J.F. p. 53-70
PDF An algorithm for finding a non-trivial lower bound for channel routing / Pal R.K., Pal S.P., Pal A. p. 71-84
PDF Erratum p. 85-87
First/Last publication year : Vol.1, no.1(Apr. 1983)-
Title language : English (eng)
ISSN : 01679260
NCID : AA10455206