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Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework

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dc.contributor.author Ahmed, Foisal en
dc.contributor.author Shintani, Michihiro en
dc.contributor.author Inoue, Michiko en
dc.date.accessioned 2021-07-19T01:57:12Z en
dc.date.available 2021-07-19T01:57:12Z en
dc.date.issued 2020-09-01 en
dc.identifier.uri http://hdl.handle.net/10061/14424 en
dc.description.abstract Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy. en
dc.language.iso en en
dc.publisher 一般社団法人電子情報通信学会 ja
dc.rights Copyright © 2020 The Institute of Electronics, Information and Communication Engineers ja
dc.subject field-programmable gate array (FPGA) en
dc.subject recycled FPGA detection en
dc.subject compressed sensing en
dc.subject FPGA fingerprinting en
dc.title Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework en
dc.type.nii Journal Article en
dc.contributor.transcription シンタニ, ミチヒロ ja
dc.contributor.transcription イノウエ, ミチコ ja
dc.contributor.alternative 新谷, 道広 ja
dc.contributor.alternative 井上, 美智子 ja
dc.textversion publisher en
dc.identifier.eissn 1745-1337 en
dc.identifier.jtitle IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences en
dc.identifier.volume E103-A en
dc.identifier.issue 9 en
dc.identifier.spage 1045 en
dc.identifier.epage 1053 en
dc.relation.doi 10.1587/transfun.2019KEP0014 en
dc.identifier.NAIST-ID 74654096 en
dc.identifier.NAIST-ID 73292369 en


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