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A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

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dc.contributor.author Yamato, Yuta en
dc.contributor.author Yoneda, Tomokazu en
dc.contributor.author Hatayama, Kazumi en
dc.contributor.author Inoue, Michiko en
dc.date.accessioned 2016-11-25T07:15:46Z en
dc.date.available 2016-11-25T07:15:46Z en
dc.date.issued 2012 en
dc.identifier.issn 1089-3539 en
dc.identifier.uri http://hdl.handle.net/10061/11174 en
dc.description ITC : 2012 IEEE International Test Conference , 5-8 Nov. 2012 , Anaheim, CA, USA en
dc.description.abstract In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency. en
dc.language.iso en en
dc.publisher IEEE en
dc.relation.isversionof http://ieeexplore.ieee.org/document/6401549/ en
dc.rights Copyright c 2012 IEEE Computer Society Washington, DC, USA en
dc.subject automatic test pattern generation en
dc.subject benchmark testing en
dc.subject infrared spectra en
dc.subject nanoelectronics en
dc.subject IR-drop-induced yield loss en
dc.subject at-speed scan test pattern validation en
dc.subject benchmark circuits en
dc.subject global cycle average power profile en
dc.subject nano-scale designs en
dc.subject per-cell dynamic IR-drop estimation method en
dc.subject representative patterns en
dc.subject supply voltage en
dc.subject total computation time en
dc.subject Clocks en
dc.subject Delay en
dc.subject Estimation en
dc.subject Power demand en
dc.subject Switches en
dc.title A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation en
dc.type.nii Conference Paper en
dc.textversion Author en
dc.identifier.spage 1 en
dc.identifier.epage 8 en
dc.relation.doi 10.1109/TEST.2012.6401549 en
dc.identifier.NAIST-ID 73292369 en
dc.identifier.NAIST-ID 73295636 en


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