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Architecting a Reliable System

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dc.contributor.author Virendra Singh ja
dc.date.accessioned 2014-09-12T08:31:50Z
dc.date.available 2014-09-12T08:31:50Z
dc.date.issued 2013-06-26 ja
dc.identifier.uri http://hdl.handle.net/10061/9821
dc.description 講演日: 平成25年6月26日 ja
dc.description 講演場所: 情報科学研究科大講義室L1 ja
dc.description.abstract Relentless scaling of silicon fabrication technology coupled with lower design tolerances are making ICs increasing susceptible to wear-out related permanent faults as well as transient faults (soft errors). A well known technique for tackling both transient and permanent faults is redundant execution, specifically space redundancy, wherein a program is executed redundantly on different processors, pipelines or functional units and the results are compared to detect faults. ja
dc.language.iso en ja
dc.publisher 奈良先端科学技術大学院大学 ja
dc.title Architecting a Reliable System ja
dc.type.nii Others ja
dc.limedio.id M010936 ja
dc.relation.ispartofcontents 情報科学研究科・ゼミナール講演 ; 平成25年度 ja
dc.contributor.affiliation Indian Institute of Technology Bombay ja
dc.publisher.alternative Nara Institute of Science and Technology ja
dc.identifier.fulltexturl https://library.naist.jp/mylimedio/dl/page.do?bookid=100085722&tocid=0&format=mp-flash ja
dc.format.time 1:33:59 ja


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