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Browsing テクニカルレポート / Technical Report by Author "Fujiwara, Hideo"

Browsing テクニカルレポート / Technical Report by Author "Fujiwara, Hideo"

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  • Iwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2004-12)
    This paper presents a transition test generation method for acyclic sequential circuits. In this method, to generate test sequences for transition faults in a given acyclic sequential circuit, constrained combinational ...
  • Yoshikawa, Yuki; Ohtake, Satoshi; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2006-02)
    In this paper, we present an approach to reduce overtesting of path delay faults (PDFs). To reduce test generation complexity, design-for-testability (DFT) techniques are used in order to make a large number of untestable ...
  • Yoneda, Tomokazu; Uchiyama, Tetsuo; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2003-02)
    Test access mechanism and test scheduling are integral parts of SoC test. This paper presents an area overhead and test time co-optimization method for SoCs based on consecutive testability. The proposed method creates TAM ...
  • Ooi, Chia Yee; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2006-07)
    This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to ...
  • Ooi, Chia Yee; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2004-01)
    Several classes of sequential circuits with combinational test generation complexity have been introduced. However, no general notation is used to define the time complexity of test generation. In this paper, we introduce ...
  • Yoneda, Tomokazu; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2002-07)
    This paper presents a design-for-consecutive-transparency method that makes a core (RTL circuit) consecutively transparent using integer linear program-ming. Consecutive transparency of a core guarantees consecutive ...
  • Yoshikawa, Yuki; Ohtake, Satoshi; Inoue, Michiko; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2005-08)
    This paper introduces a new concept of hierarchical testability called Single-Port-Change (SPC) two-pattern testability. We propose a non-scan design-for-testability (DFT) method which makes each path that needs to be ...
  • Iwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2003-09)
    This paper proposes a non-scan testing scheme to enhance delay fault testability of controllers. In this scheme, the original behavior of a given controller is used in test application, and the faults which cannot be ...
  • Yoneda, Tomokazu; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2001-05)
    This paper proposes a new methodology for testing a core-based systems-on-a-chip (SoC) based on a new concept of testability called consecutive testability. In the proposed method, test sequence of a core embedded deep in ...
  • Inoue, Michiko; Nakazato, Masato; Yokoyama, Shinya; Kambe, Kazuko; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2006-08)
    This paper presents a method of test program generation for software-based self-test of pipelined processors. We propose a model of pipelined processors and testability measures for registers. We generate a test program ...
  • Gizdarski, Emil; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2001-03)
    In this paper, we present a technique for reducing the test length of the counter-based pseudo-exhaustive built-in self-testing (BIST) using the width compression method and the divide-and-conquer strategy. More formally, ...
  • Yoneda, Tomokazu; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2002-02)
    This paper introduces a new concept called consecutive testability and proposes a design-for-testability method that makes a given SoC consecutively testable using integer lin-ear programming (ILP). A consecutively testable ...
  • Ooi, Chia Yee; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2006-05)
    This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to ...
  • Gizdarski, Emil; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2000-01)
    In this paper we analyze learning techniques based on the Boolean satisfiability method and find that static indirect ∧-implications and the super gate extraction are useful for increasing the precision of low complexity ...
  • Das, Debesh Kumar; Ohtake, Satoshi; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 1998-11)
    As opposed to scan schemes, non-scan DFT allows at-speed testing. This paper suggests three techniques on non-scan DFT of sequential circuits. The novelty of the proposed techniques is that by using combinational ATPG tool ...
  • Ohtake, Satoshi; Nagai, Shintaro; Wada, Hiroki; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2000-11)
    This paper proposes a non-scan design-for-test-ability method for register-transfer level circuits where a cir-cuit consists of a controller and a data path. It achieves com-plete fault efficiency with low hardware overhead ...
  • Larsson, Erik; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2002-07)
    In this paper, we show that the test access mechanism (TAM) scheduling is equal to the independent job scheduling on independent machines. We make use of an existing preemptive scheduling algorithm, which produces an optimal ...
  • Yoshikawa, Yuki; Ohtake, Satoshi; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2007-06)
    While design-for-testability (DFT) techniques are generally used in order to reduce test generation complexity, they induce over-testing problems. In general, DFT techniques make a large number of untestable paths testable. ...
  • Yoneda, Tomokazu; Masuda, Kimihiko; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2005-06)
    This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a test scheduling algorithm for multi-clock ...
  • Larsson, Erik; Fujiwara, Hideo (Nara Institute of Science and Technology奈良先端科学技術大学院大学, 2002-01)
    We investigate power constrained test access mechanism (TAM) scheduling for core-based system by combining scan-chain partitioning and preemption. We discuss scan-chain partitioning in core-based design to minimize test ...

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