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General Architecture for Hardware Implementation of Genetic Algorithm

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dc.contributor.author Tachibana, Tatsuhiro
dc.contributor.author Murata, Yoshihiro
dc.contributor.author Shibata, Naoki
dc.contributor.author Yasumoto, Keiichi
dc.contributor.author Ito, Minoru
dc.date.accessioned 2017-01-10T07:31:55Z
dc.date.available 2017-01-10T07:31:55Z
dc.date.issued 2006
dc.identifier.uri http://hdl.handle.net/10061/11367
dc.description FCCM 2006 : 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines , Apr 24-26, 2006 , Napa, CA, USA
dc.description.abstract In this paper, the authors propose a technique to flexibly implement genetic algorithms (GAs) for various problems on FPGAs. For the purpose, the authors propose a common architecture for GA. The proposed architecture allows designers to easily implement a GA as a hardware circuit consisting of parallel pipelines which execute GA operations. The proposed architecture is scalable to increase the number of parallel pipelines. The architecture is applicable to various problems and allows designers to estimate the size of resulting circuits. The authors give a model for predicting the size of resulting circuits from given parameters. Based on the proposed method, the authors have implemented a tool to facilitate GA circuit design and development. Through experiments using knapsack problem and traveling salesman problem (TSP), the authors show that the FPGA circuits synthesized based on the proposed method run much faster and consume much lower power than software implementation on a PC and the model can predict the size of the resulting circuit accurately enough.
dc.language.iso en
dc.publisher IEEE
dc.rights Copyright c 2006 IEEE Computer Society Washington, DC, USA
dc.subject field programmable gate arrays
dc.subject genetic algorithms
dc.subject logic design
dc.subject parallel architectures
dc.subject FPGA
dc.subject circuit design
dc.subject circuit synthesis
dc.subject genetic algorithm
dc.subject hardware circuit
dc.subject hardware implementation
dc.subject knapsack problem
dc.subject parallel pipelines
dc.subject size prediction
dc.subject software implementation
dc.subject traveling salesman problem
dc.subject Biological cells
dc.subject Circuits
dc.subject Clocks
dc.subject Computer architecture
dc.subject Field programmable gate arrays
dc.subject Genetic algorithms
dc.subject Genetic mutations
dc.subject Hardware
dc.subject Pipelines
dc.subject Predictive models
dc.title General Architecture for Hardware Implementation of Genetic Algorithm
dc.type.nii Conference Paper
dc.textversion Author
dc.identifier.spage 291
dc.identifier.epage 292
dc.relation.doi 10.1109/FCCM.2006.43
dc.identifier.NAIST-ID 73292302
dc.identifier.NAIST-ID 22740047
dc.identifier.NAIST-ID 73292559

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