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A Hardware Implementation Method of Multi-Objective Genetic Algorithms

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dc.contributor.author Tachibana, Tatsuhiro
dc.contributor.author Murata, Yoshihiro
dc.contributor.author Shibata, Naoki
dc.contributor.author Yasumoto, Keiichi
dc.contributor.author Ito, Minoru
dc.date.accessioned 2017-01-10T07:31:52Z
dc.date.available 2017-01-10T07:31:52Z
dc.date.issued 2006
dc.identifier.uri http://hdl.handle.net/10061/11345
dc.description CEC2006 : IEEE International Conference on Evolutionary Computation , Jul 16-21, 2006 , Vancouver, BC, Canada
dc.description.abstract Multi-objective genetic algorithms (MOGAs) are approximation techniques to solve multi-objective optimization problems. Since MOGAs search a wide variety of pareto optimal solutions at the same time, MOGAs require large computation power. In order to solve practical sizes of the multi objective optimization problems, it is desirable to design and develop a hardware implementation method for MOGAs with high search efficiency and calculation speed. In this paper, we propose a new method to easily implement MOGAs as high performance hardware circuits. In the proposed method, we adopt simple Minimal Generation Gap (MGG) model as the generation model, because it is easy to be pipelined. In order to preserve diversity of individuals, we need a special selection mechanism such as the niching method which takes large computation time to repeatedly compare superiority among all individuals in the population. In the proposed method, we developed a new selection mechanism which greatly reduces the number of comparisons among individuals, keeping diversity of individuals. Our method also includes a parallel execution architecture based on Island GA which is scalable to the number of concurrent pipelines and effective to keep diversity of individuals. We applied our method to multi-objective Knapsack Problem. As a result, we confirmed that our method has higher search efficiency than existing method.
dc.language.iso en
dc.publisher IEEE
dc.rights Copyright c 2006 IEEE Computer Society Washington, DC, USA
dc.subject Pareto optimisation
dc.subject approximation theory
dc.subject genetic algorithms
dc.subject knapsack problems
dc.subject pipeline processing
dc.subject approximation techniques
dc.subject concurrent pipelines
dc.subject hardware circuits
dc.subject hardware implementation method
dc.subject island GA
dc.subject minimal generation gap
dc.subject multiobjective genetic algorithms
dc.subject multiobjective knapsack problem
dc.subject niching method
dc.subject pareto optimal solutions
dc.subject special selection mechanism
dc.subject Ant colony optimization
dc.subject Circuits
dc.subject Field programmable gate arrays
dc.subject Genetic algorithms
dc.subject Hardware
dc.subject Indium tin oxide
dc.subject Information processing
dc.subject Information science
dc.subject Pipelines
dc.subject Steady-state
dc.title A Hardware Implementation Method of Multi-Objective Genetic Algorithms
dc.type.nii Conference Paper
dc.identifier.fulltexturl http://ieeexplore.ieee.org/document/1688708/?denied
dc.textversion Author
dc.identifier.spage 3153
dc.identifier.epage 3160
dc.relation.doi 10.1109/CEC.2006.1688708
dc.identifier.NAIST-ID 73292302
dc.identifier.NAIST-ID 22740047
dc.identifier.NAIST-ID 73292559

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