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Power-aware test generation with guaranteed launch safety for at-speed scan testing

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dc.contributor.author Wen, Xiaoqing
dc.contributor.author Enokimoto, Kazunari
dc.contributor.author Miyase, Kohei
dc.contributor.author Yamato, Yuta
dc.contributor.author Michael A. Kochte
dc.contributor.author Kajihara, Seiji
dc.contributor.author Girard, Patrick
dc.contributor.author Tehranipoor, Mohammad
dc.date.accessioned 2016-11-25T07:15:47Z
dc.date.available 2016-11-25T07:15:47Z
dc.date.issued 2011
dc.identifier.issn 1093-0167
dc.identifier.uri http://hdl.handle.net/10061/11179
dc.description VTS : 2011 IEEE 29th VLSI Test Symposium , 1-5 May. 2011 , Dana Point, CA, USA
dc.description.abstract At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by excessive launch switching activity (LSA) caused by test stimulus launching in the at-speed test cycle. However, previous low-power test generation techniques can only reduce LSA to some extent but cannot guarantee launch safety. This paper proposes a novel & practical power-aware test generation flow, featuring guaranteed launch safety. The basic idea is to enhance ATPG with a unique two-phase (rescue & mask) scheme by targeting at the real cause of the launch safety problem, i.e., the excessive LSA in the neighboring areas (namely impact areas) around long paths sensitized by a test vector. The rescue phase is to reduce excessive LSA in impact areas in a focused manner, and the mask phase is to exclude from use in fault detection the uncertain test response at the endpoint of any long sensitized path that still has excessive LSA in its impact area even after the rescue phase is executed. This scheme is the first of its kind for achieving guaranteed launch safety with minimal impact on test quality and test costs, which is the ultimate goal of power-aware at-speed scan test generation.
dc.language.iso en
dc.publisher IEEE
dc.rights Copyright c 2011 IEEE Computer Society Washington, DC, USA
dc.subject automatic test pattern generation
dc.subject fault diagnosis
dc.subject logic testing
dc.subject ATPG
dc.subject at-speed scan testing
dc.subject fault detection
dc.subject guaranteed launch safety
dc.subject launch switching activity
dc.subject low-power test generation
dc.subject power-aware test generation
dc.subject rescue & mask scheme
dc.subject Automatic test pattern generation
dc.subject Circuit faults
dc.subject Compaction
dc.subject Fault detection
dc.subject Lead
dc.subject Safety
dc.subject at-speed scan testing
dc.subject launch safety
dc.subject power supply noise
dc.subject test generation
dc.subject test power
dc.title Power-aware test generation with guaranteed launch safety for at-speed scan testing
dc.type.nii Conference Paper
dc.identifier.fulltexturl http://ieeexplore.ieee.org/document/5783778/
dc.textversion Author
dc.identifier.spage 166
dc.identifier.epage 171
dc.relation.doi 10.1109/VTS.2011.5783778
dc.identifier.NAIST-ID 73295636


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