Yamato, Yuta; Wen, Xiaoqing; Michael A. Kochte; Miyase, Kohei; Kajihara, Seiji; Wang, Laung-Terng
(IEEE, 2011)
High power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which ...