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Browsing by Author Ohtake, Satoshi

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Issue DateTitleAuthor(s)
Dec-2004Acceleration of transition test generation for acyclic sewuential circuits utilizing constrained combinational stuck-at test generationIwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo
Feb-2006An approach to reduce over-testing of path delay faults in data paths using RT-level informationYoshikawa, Yuki; Ohtake, Satoshi; Fujiwara, Hideo
Aug-2005Design for testability based on single-port-change delay testing for data pathsYoshikawa, Yuki; Ohtake, Satoshi; Inoue, Michiko; Fujiwara, Hideo
Sep-2003A design scheme for delay fault testability of controllers using state transition informationIwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo
Nov-1998New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault EfficiencyDas, Debesh Kumar; Ohtake, Satoshi; Fujiwara, Hideo
Nov-2000An Non-scan DFT Method at RTL Based on Fixed-control Testability to Achieve 100% Fault EfficiencyOhtake, Satoshi; Nagai, Shintaro; Wada, Hiroki; Fujiwara, Hideo
Jun-2007Over-testing reduction for delay faults through false path exclusion using RTL informationYoshikawa, Yuki; Ohtake, Satoshi; Fujiwara, Hideo
Sep-2003Reducibility of sequential test generation to combinational test generation for several delay fault modelsIwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo
Jul-1997Sequential test generation based on circuit pseudo-transformationOhtake, Satoshi; Inoue, Tomoo; Fujiwara, Hideo
Showing results 1 to 9 of 9

 

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