|
|
naistar (NAIST Academic Repository) >
Browsing by Author Ohtake, Satoshi
Showing results 1 to 9 of 9
| Issue Date | Title | Author(s) | | Dec-2004 | Acceleration of transition test generation for acyclic sewuential circuits utilizing constrained combinational stuck-at test generation | Iwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo |
| Feb-2006 | An approach to reduce over-testing of path delay faults in data paths using RT-level information | Yoshikawa, Yuki; Ohtake, Satoshi; Fujiwara, Hideo |
| Aug-2005 | Design for testability based on single-port-change delay testing for data paths | Yoshikawa, Yuki; Ohtake, Satoshi; Inoue, Michiko; Fujiwara, Hideo |
| Sep-2003 | A design scheme for delay fault testability of controllers using state transition information | Iwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo |
| Nov-1998 | New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency | Das, Debesh Kumar; Ohtake, Satoshi; Fujiwara, Hideo |
| Nov-2000 | An Non-scan DFT Method at RTL Based on Fixed-control Testability to Achieve 100% Fault Efficiency | Ohtake, Satoshi; Nagai, Shintaro; Wada, Hiroki; Fujiwara, Hideo |
| Jun-2007 | Over-testing reduction for delay faults through false path exclusion using RTL information | Yoshikawa, Yuki; Ohtake, Satoshi; Fujiwara, Hideo |
| Sep-2003 | Reducibility of sequential test generation to combinational test generation for several delay fault models | Iwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo |
| Jul-1997 | Sequential test generation based on circuit pseudo-transformation | Ohtake, Satoshi; Inoue, Tomoo; Fujiwara, Hideo |
Showing results 1 to 9 of 9
|
