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naistar (NAIST Academic Repository) >
Browsing by Author Fujiwara, Hideo
Showing results 1 to 20 of 34
| Issue Date | Title | Author(s) | | Dec-2004 | Acceleration of transition test generation for acyclic sewuential circuits utilizing constrained combinational stuck-at test generation | Iwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo |
| Feb-2006 | An approach to reduce over-testing of path delay faults in data paths using RT-level information | Yoshikawa, Yuki; Ohtake, Satoshi; Fujiwara, Hideo |
| Feb-2003 | Area and time co-optimization for system-on-a-chip based on consecutive testability | Yoneda, Tomokazu; Uchiyama, Tetsuo; Fujiwara, Hideo |
| Jul-2006 | Classification of sequential circuits based on acyclic test generation complexity | Ooi, Chia Yee; Fujiwara, Hideo |
| Jan-2004 | Classification of sequential circuits based on combinational test generation complexity | Ooi, Chia Yee; Fujiwara, Hideo |
| Jul-2002 | Design for consecutive transparency of RTL circuits | Yoneda, Tomokazu; Fujiwara, Hideo |
| Aug-2005 | Design for testability based on single-port-change delay testing for data paths | Yoshikawa, Yuki; Ohtake, Satoshi; Inoue, Michiko; Fujiwara, Hideo |
| Sep-2003 | A design scheme for delay fault testability of controllers using state transition information | Iwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo |
| May-2001 | A DFT method for core-based systems-on-a-chip based on consecutive testability | Yoneda, Tomokazu; Fujiwara, Hideo |
| Aug-2006 | Efficient and effective test program generation for software-based self-test of pipelined processors | Inoue, Michiko; Nakazato, Masato; Yokoyama, Shinya; Kambe, Kazuko; Fujiwara, Hideo |
| Jan-2009 | Efficient Mutual Exclusion Algorithm for High System Congestion | Suzuki, Tsuyoshi; Inoue, Michiko; Fujiwara, Hideo |
| Mar-2001 | Fault set partition for efficient width compression | Gizdarski, Emil; Fujiwara, Hideo |
| Feb-2002 | An ILP formulation for consecutive testability of system-on-a-chip | Yoneda, Tomokazu; Fujiwara, Hideo |
| May-2006 | A new class of sequential circuits with acyclic test generation complexity | Ooi, Chia Yee; Fujiwara, Hideo |
| Jan-2000 | A New Data Structure for Complete Implication Graph with Application for Static Learning | Gizdarski, Emil; Fujiwara, Hideo |
| Nov-1998 | New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency | Das, Debesh Kumar; Ohtake, Satoshi; Fujiwara, Hideo |
| Nov-2000 | An Non-scan DFT Method at RTL Based on Fixed-control Testability to Achieve 100% Fault Efficiency | Ohtake, Satoshi; Nagai, Shintaro; Wada, Hiroki; Fujiwara, Hideo |
| Jul-2002 | Optimal test time for system-on-chip designs using preemptive scheduling and reconfigurable wrappers | Larsson, Erik; Fujiwara, Hideo |
| Jun-2007 | Over-testing reduction for delay faults through false path exclusion using RTL information | Yoshikawa, Yuki; Ohtake, Satoshi; Fujiwara, Hideo |
| Jun-2005 | Power-constrained test scheduling for multi-clock domain SoCs | Yoneda, Tomokazu; Masuda, Kimihiko; Fujiwara, Hideo |
Showing results 1 to 20 of 34
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