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Browsing by Author Fujiwara, Hideo

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Issue DateTitleAuthor(s)
Dec-2004Acceleration of transition test generation for acyclic sewuential circuits utilizing constrained combinational stuck-at test generationIwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo
Feb-2006An approach to reduce over-testing of path delay faults in data paths using RT-level informationYoshikawa, Yuki; Ohtake, Satoshi; Fujiwara, Hideo
Feb-2003Area and time co-optimization for system-on-a-chip based on consecutive testabilityYoneda, Tomokazu; Uchiyama, Tetsuo; Fujiwara, Hideo
Jul-2006Classification of sequential circuits based on acyclic test generation complexityOoi, Chia Yee; Fujiwara, Hideo
Jan-2004Classification of sequential circuits based on combinational test generation complexityOoi, Chia Yee; Fujiwara, Hideo
Jul-2002Design for consecutive transparency of RTL circuitsYoneda, Tomokazu; Fujiwara, Hideo
Aug-2005Design for testability based on single-port-change delay testing for data pathsYoshikawa, Yuki; Ohtake, Satoshi; Inoue, Michiko; Fujiwara, Hideo
Sep-2003A design scheme for delay fault testability of controllers using state transition informationIwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo
May-2001A DFT method for core-based systems-on-a-chip based on consecutive testabilityYoneda, Tomokazu; Fujiwara, Hideo
Aug-2006Efficient and effective test program generation for software-based self-test of pipelined processorsInoue, Michiko; Nakazato, Masato; Yokoyama, Shinya; Kambe, Kazuko; Fujiwara, Hideo
Jan-2009Efficient Mutual Exclusion Algorithm for High System CongestionSuzuki, Tsuyoshi; Inoue, Michiko; Fujiwara, Hideo
Mar-2001Fault set partition for efficient width compressionGizdarski, Emil; Fujiwara, Hideo
Feb-2002An ILP formulation for consecutive testability of system-on-a-chipYoneda, Tomokazu; Fujiwara, Hideo
May-2006A new class of sequential circuits with acyclic test generation complexityOoi, Chia Yee; Fujiwara, Hideo
Jan-2000A New Data Structure for Complete Implication Graph with Application for Static LearningGizdarski, Emil; Fujiwara, Hideo
Nov-1998New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault EfficiencyDas, Debesh Kumar; Ohtake, Satoshi; Fujiwara, Hideo
Nov-2000An Non-scan DFT Method at RTL Based on Fixed-control Testability to Achieve 100% Fault EfficiencyOhtake, Satoshi; Nagai, Shintaro; Wada, Hiroki; Fujiwara, Hideo
Jul-2002Optimal test time for system-on-chip designs using preemptive scheduling and reconfigurable wrappersLarsson, Erik; Fujiwara, Hideo
Jun-2007Over-testing reduction for delay faults through false path exclusion using RTL informationYoshikawa, Yuki; Ohtake, Satoshi; Fujiwara, Hideo
Jun-2005Power-constrained test scheduling for multi-clock domain SoCsYoneda, Tomokazu; Masuda, Kimihiko; Fujiwara, Hideo
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